803 research outputs found

    What every ICU clinician needs to know about the cardiovascular effects caused by abdominal hypertension

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    The effects of increased intra-abdominal pressure (IAP) on cardiovascular function are well recognized and include a combined negative effect on preload, afterload and contractility. The aim of this review is to summarize the current knowledge on this topic. The presence of intra-abdominal hypertension (IAH) erroneously increases barometric filling pressures like central venous (CVP) and pulmonary artery occlusion pressure (PAOP) (since these are zeroed against atmospheric pressure). Transmural filling pressures (calculated by subtracting the pleural pressure from the end-expiratory CVP value) may better reflect the true preload status but are difficult to obtain at the bedside. Alternatively, since pleural pressures are seldom measured, transmural CVP can also be estimated by subtracting half of the IAP from the end-expiratory CVP value, since abdominothoracic transmission is on average 50%. Volumetric preload indicators, such as global and right ventricular end-diastolic volumes or the left ventricular end-diastolic area, also correlate better with true preload. When using functional hemodynamic monitoring parameters like stroke volume variation (SVV) or pulse pressure variation (PPV) one must bear in mind that increased IAP will increase these values (via a concomitant increase in intrathoracic pressure). The passive leg raising test may be a false negative in IAH. Calculation of the abdominal perfusion pressure (as mean arterial pressure minus IAP) has been shown to be a better resuscitation endpoint than IAP alone. Finally, it is re-assuring that transpulmonary thermodilution techniques have been validated in the setting of IAH and abdominal compartment syndrome. In conclusion, the clinician must be aware of the different effects of IAH on cardiovascular function in order to assess the volume status accurately and to optimize hemodynamic performance

    Link-time smart card code hardening

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    This paper presents a feasibility study to protect smart card software against fault-injection attacks by means of link-time code rewriting. This approach avoids the drawbacks of source code hardening, avoids the need for manual assembly writing, and is applicable in conjunction with closed third-party compilers. We implemented a range of cookbook code hardening recipes in a prototype link-time rewriter and evaluate their coverage and associated overhead to conclude that this approach is promising. We demonstrate that the overhead of using an automated link-time approach is not significantly higher than what can be obtained with compile-time hardening or with manual hardening of compiler-generated assembly code

    A digitally controlled threshold adjustment circuit in a 0.13um SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

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    In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13µm SiGe BiCMOS technology and a threshold tunable between ±160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a data rate of up to 80Gbps can be achieved

    A duobinary receiver chip for 84 Gb/s serial data communication

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    SCM : Secure Code Memory Architecture

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    An increasing number of applications implemented on a SoC (System-on-chip) require security features. This work addresses the issue of protecting the integrity of code and read-only data that is stored in memory. To this end, we propose a new architecture called SCM, which works as a standalone IP core in a SoC. To the best of our knowledge, there exist no architectural elements similar to SCM that offer the same strict security guarantees while, at the same time, not requiring any modifications to other IP cores in its SoC design. In addition, SCM has the flexibility to select the parts of the software to be protected, which eases the integration of our solution with existing software. The evaluation of SCM was done on the Zynq platform which features an ARM processor and an FPGA. The design was evaluated by executing a number of different benchmarks from memory protected by SCM, and we found that it introduces minimal overhead to the system

    56+ Gb/s serial transmission using duo-binary signaling

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    In this paper we present duobinary signaling as an alternative for signaling schemes like PAM4 and Ensemble NRZ that are currently being considered as ways to achieve data rates of 56 Gb/s over copper. At the system level, the design includes a custom transceiver ASIC. The transmitter is capable of equalizing 56 Gb/s non-return to zero (NRZ) signals into a duobinary response at the output of the channel. The receiver includes dedicated hardware to decode the duobinary signal. This transceiver is used to demonstrate error-free transmission for different PCB channel lengths including a state-of-the-art Megtron 6 backplane demonstrator

    SOFIA : software and control flow integrity architecture

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    Microprocessors used in safety-critical systems are extremely sensitive to software vulnerabilities, as their failure can lead to injury, damage to equipment, or environmental catastrophe. This paper proposes a hardware-based security architecture for microprocessors used in safety-critical systems. The proposed architecture provides protection against code injection and code reuse attacks. It has mechanisms to protect software integrity, perform control flow integrity, prevent execution of tampered code, and enforce copyright protection. We are the first to propose a mechanism to enforce control flow integrity at the finest possible granularity. The proposed architectural features were added to the LEON3 open source soft microprocessor, and were evaluated on an FPGA running a software benchmark. The results show that the hardware area is 28.2% larger and the clock is 84.6% slower, while the software benchmark has a cycle overhead of 13.7% and a total execution time overhead of 110% when compared to an unmodified processor

    Illumina sequencing of 15 deafness genes using fragmented amplicons

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    BACKGROUND: Resequencing of deafness related genes using GS FLX massive parallel sequencing of PCR amplicons spanning selected genes has previously been reported as a successful strategy to discover causal variants. The amplicon lengths were designed to be smaller than the sequencing read length of GS FLX technology, but are longer than Illumina sequencing technology read lengths. Fragmentation is thus required to sequence these amplicons using high throughput Illumina technology. METHODS: We performed Illumina sequencing in 4 patients on 563 multiplexed amplicons covering the exons of 15 genes involved in the hearing process. After exploring several fragmentation strategies, the amplicons were fragmented using Covaris sonication prior to library preparation. CLC genomic workbench was used to analyze the data. RESULTS: We achieve an excellent coverage with more than 99% of the amplicons bases covered. All variants that were previously validated using Sanger sequencing, were also called in this study. Variant calling revealed less false positive and false negative results compared to the previous study. For each patient, several variants were found that are reported by ClinVar as possible hearing loss variants. CONCLUSION: Migration from GS FLX amplicon sequencing to Illumina amplicon sequencing is straightforward and leads to more accurate results. ELECTRONIC SUPPLEMENTARY MATERIAL: The online version of this article (doi:10.1186/1756-0500-7-509) contains supplementary material, which is available to authorized users

    Development and performance of a targeted whole exome sequencing enrichment kit for the dog (Canis Familiaris Build 3.1)

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    Whole exome sequencing is a technique that aims to selectively sequence all exons of protein-coding genes. A canine whole exome sequencing enrichment kit was designed based on the latest canine reference genome (build 3.1.72). Its performance was tested by sequencing 2 exome captures, each consisting of 4 pre-capture pooled, barcoded Illumina libraries on an Illumina HiSeq 2500. At an average sequencing depth of 102x, 83 to 86% of the target regions were completely sequenced with a minimum coverage of five and 90% of the reads mapped on the target regions. Additionally, it is shown that the reproducibility within and between captures is high and that pooling four samples per capture is a valid option. Overall, we have demonstrated the strong performance of this WES enrichment kit and are confident it will be a valuable tool in future disease association studies
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